1. Field of the Invention
The present invention relates to a method of reducing an optical proximity effect; more particularly, the present invention relates to an improved photolithography method for reducing the optical proximity effect of an exposed pattern which occurred during a conventional photolithography process.
2. Description of the Prior Art
In recent years, the size of a semiconductor device has been decreased as in proportion to the developments of the semiconductor IC design rule and the photolithography technology. For example, most of the semiconductor photolithography processes nowadays apply the latest i-line or deep ultra violet (DUV) photolithography system to fabricate semiconductor devices of extremely small dimensions. However, if the linewidth of the fabricated integrated circuits (IC) in a semiconductor device is equal to or smaller than the wavelength of a light source provided for carrying through the photolithography processes, the optical proximity effect emerges such that an incorrect or undesirable exposed pattern size on a photoresist layer is obtained. Further, the allowable critical dimension tolerance according to the conventional photolithography process is decreased because of the optical proximity effect, which inevitably increases the complexity of said photolithography process.
The so-called optical proximity effect (OPE) is an optical condition in which an undesirable pattern transfer (for example, a pattern shrinkage) is performed during a conventional photolithography process. Said undesirable pattern transfer involves incorrectly projecting an etch pattern of a photomask onto a photoresist layer by a stepper, which is generally caused by a light reflection, refraction, or diffraction effect which occurred during the photolithography process. Referring to FIG. 1, a top view of an undesirable pattern transfer formed by a conventional photolithography process affected by the OPE is shown, wherein the etch pattern 10 of a photomask does not exactly correspond to the exposed pattern 12 of a photoresist layer. The sharp corners of the etch pattern 10 of the photomask (not shown) become rounded after being projected onto the photoresist layer (not shown) because scattering light blurs out the distinct edges and corners of the mask pattern 10. As a consequence, normal operations of the IC formed based on the incorrectly exposed pattern 12 may be adversely affected.
Typically, the optical proximity effect can be partially compensated by amending the patterns on the photomask. For example, if it is known that an image formed on a photoresist layer is narrower than the desired pattern, the pattern on the photomask may be designed to be wider than the original size. Referring to FIG. 2, the top view of a partially compensated pattern is shown constituting the etch pattern 20 of a photomask. Then, a plurality of pattern-correcting hammerheads 24, which are collectively called a mask bias, are added to the corner edges of the photomask pattern 20 as shown in FIG. 2. Subsequently, the photomask pattern 20 is exposed under the light source of a stepper (not shown) to be transferred onto a photoresist layer (not shown) during a photolithography process so that an accurate exposed pattern 22 is formed. As described above, the hammerheads 24 are added to the corner edges of the etch pattern 20 of a photomask to increase the corner areas of the exposed pattern 22. Thus, the exposed pattern 22 on the photoresist layer is sufficiently compensated by employing the mask bias to correct the pattern shrinkage phenomenon caused by scattering light. Thereafter, a relevant data set containing all parameter corrections of the etch pattern 20 on a photomask as well as other parameters used for optimizing a photolithography process are entered into a computer as a database for correcting more photolithography processes and photomask etch patterns. It is called auto optical proximity correction (OPC).
In addition, other conventional methods for reducing the optical proximity effect also include a method of adjusting the stepper used in a conventional photolithography process so that the aperture, coherence, intensity of energy, and/or contrast of an exposed pattern on a photoresist layer are optimized to meet the requirements of critical dimensions.
However, since the line width or the line pitch that defines the IC layout of a semiconductor device has been decreased to a point that the space between these line widths may not be sufficient for the hammerheads to be added to. Thus, the corrections made by these compensated patterns 20 on the photomasks, as described above, are limitative such that further development of the photolithography technology is restricted by the extent of the mask bias.
Moreover, since integrated circuits (IC) of different line pitches are almost always integrated on a same semiconductor device or chip, it is therefore very difficult to transfer an etch pattern with different line pitches onto a photoresist layer while trying to meet the critical dimensions of all line pitches by simply adjusting the numerical aperture, coherence, intensity of energy, and/or contrast of a stepper.
Accordingly, it is an object of the present invention to provide a method of reducing an optical proximity effect (OPE) without using any additional mask bias to transfer an etch pattern from a photomask to a photoresist layer more precisely during a photolithography process; in addition, the OPEs inherent to the different line pitches of an exposed pattern on a photoresist layer are compensated by adjusting the operating parameters of a stepper such as the numerical aperture, coherence, intensity of energy, and/or contrast.
To achieve the above-described object, the present invention provides a method of reducing the OPE by dividing an etch pattern that corresponds to the IC layout pattern of a semiconductor device into a plurality of sub-patterns, wherein each of the sub-patterns comprises a portion of the etch pattern having a particular line pitch. Then, a plurality of such sub-patterns are each formed on a corresponding photomask to be sequentially transferred to a photoresist layer during a photolithography process to complete an overall exposed pattern.
Moreover, the method of reducing the OPE according to the present invention is comprised of the following steps. First, a primary pattern that corresponds to the overall IC layout pattern of a semiconductor device is provided. The primary pattern is then divided into a plurality of sub-patterns each comprising a portion of the primary pattern having a particular line pitch. Subsequently, a plurality of such sub-patterns are each formed on a corresponding photomask to be sequentially transferred to a photoresist layer by means of a stepper during a photolithography process to complete an overall exposed pattern. A light source is provided by the stepper so that the sub-patterns formed on corresponding photomasks can be transferred sequentially onto the photoresist layer by passing the light from the light source through the photomasks.
It is noted that since each sub-pattern is comprised of a portion of the primary pattern formed on a corresponding photomask having a particular line pitch according to the present invention, the OPE inherent to each of the sub-patterns thus can be suitably compensated by adjusting the values of numerical aperture, coherence, intensity of energy, and/or contrast to individually meet the critical dimension of each sub-pattern. Therefore, an etch pattern with different line pitches can be successfully transferred onto a photoresist layer with each critical dimension of the different line pitches accurately met according to the present invention.